Sehemu ya hisa.: 1842
Andika: Clock Generator, Fanout Distribution, Zero Delay Buffer, PLL: Yes with Bypass, Ingizo: HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL, Pato: eHSTL, HSTL, LVCMOS, LVTTL, SSTL, Idadi ya Mizunguko: 1, Uwiano - Pembejeo: Pato: 2:20,