| Andika | Maelezo. |
| Hali ya Sehemu | Active |
|---|---|
| Andika | Interface |
| Kazi | Data Capture |
| Iliyoingizwa | Yes, FPGA / CPLD |
| Iliyotumiwa IC / Sehemu | - |
| Sifa za Msingi | ADC and DAC Evaluation |
| Yaliyotolewa | Board(s), Cable(s) |
| Hali ya RoHS. | Rohs inakubaliana. |
|---|---|
| Ngazi ya unyeti wa unyevu (MSL) | Haitumiki |
| Hali ya LifeCycle. | Kizamani / mwisho wa maisha. |
| Stock Jamii. | Inapatikana hisa. |